LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;

entity TP1 is
  port( 
  ck: in std_logic;
  rst: in std_logic;
  displayNumerico: out std_logic_vector(7 downto 0);
  selector: out std_logic_vector(3 downto 0)
  );
end;

architecture aTP1 of TP1 is
  component ContadorBCD4Digitos is
port(
	rst : in std_logic;
	ck: in std_logic;
	q0 : out std_logic_vector(3 downto 0);
	q1 : out std_logic_vector(3 downto 0);
	q2 : out std_logic_vector(3 downto 0);
	q3 : out std_logic_vector(3 downto 0)
	);
	
  end component;
  
  component ControladorDisplay7seg is
  port(
  rst:  in std_logic;
  bcd3,bcd2,bcd1,bcd0 : in std_logic_vector (3 downto 0);
  ck  : in std_logic;
  displayNumerico: out std_logic_vector(7 downto 0);
  selector: out std_logic_vector(3 downto 0)
  );
  end component;
  
  signal bcd3: std_logic_vector(3 downto 0);
  signal bcd2: std_logic_vector(3 downto 0);
  signal bcd1: std_logic_vector(3 downto 0);
  signal bcd0: std_logic_vector(3 downto 0);
  
begin
cont: ContadorBCD4Digitos port map (rst , ck , bcd3 , bcd2, bcd1, bcd0);
controlador: ControladorDisplay7seg port map (rst,bcd3,bcd2,bcd1,bcd0,ck,displayNumerico,selector); 
end;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;

entity testTP1 is
end;

architecture atestTP1 of testTP1 is
  component TP1 is
  port( ck: in std_logic;
  rst: in std_logic;
  displayNumerico: out std_logic_vector(7 downto 0);
  selector: out std_logic_vector(3 downto 0)
  );
  end component;
  signal ck_s : std_logic:= '0';
  signal clr_s : std_logic:= '1';
  signal displayNumerico_s: std_logic_vector(7 downto 0);
  signal selector_s: std_logic_vector(3 downto 0);
  
begin
clr_s <= '0' after 50 ns;
ck_s <= not ck_s after 10 ns;
tp: TP1 port map (ck_s , clr_s , displayNumerico_s, selector_s);   
end;

